;-------------------------------------------------------------------------- ; ; PEEDI target configuration file for NXP MIMXRT1064-EVK (Cortex-M7) ; ; i.MX RT1064 ; ;-------------------------------------------------------------------------- ; The following section contains licenses that are required for PEEDI to ; operate. These licenses must be filled before using this file. ; The [LICENSE] section may contain license keys for one or more PEEDIs. ; ; Example: ; [LICENSE] ; KEY = UPDATE_24MAY2010, 1111-1111-1111-1 ; KEY = XXXXX, 2222-2222-2222-2 ; ; The [LICENSE] section may point to an external file which contains ; license keys for one or more PEEDIs. The external file must include ; the text [LICENSE] followed by all keys. ; ; Example: ; [LICENSE] ; FILE = tftp://192.168.3.1/license.txt ; or ; FILE=eep:license.txt ; or ; FILE = ftp://user:password@192.168.3.1/license.txt ; ; ; PEEDI is shipped with license keys stored in "eep:license.txt" and ; printed on a label on the bottom side of PEEDI. ; [LICENSE] FILE = eep:license.txt ;-------------------------------------------------------------------------- [DEBUGGER] PROTOCOL = gdb_remote ; gdb remote REMOTE_PORT = 9000 ; TCP/IP port FLASH = FLASH_RT1064_F2 ; used when programming via gdb ;FLASH = FLASH_RT1064_F1 ; used when programming via gdb [TARGET] PLATFORM = Cortex-M_SWD [PLATFORM_Cortex-M_SWD] SWD_CLOCK = 4000 ; SWD Clock in [kHz] TRST_TYPE = OPENDRAIN ; type of TRST output: OPENDRAIN or PUSHPULL RESET_TIME = 20 ; length of RESET pulse in ms; 0 means no RESET TIME_AFTER_RESET = 10 CORE0 = Cortex-M ; TAP is actually CortexM7 CPU CORE0_RESET_MODE = vectreset CORE0_STARTUP_MODE = RESET ; stop the core immediately after reset CORE0_ENDIAN = LITTLE ; core is little endian CORE0_BREAKMODE = SOFT ; breakpoint mode: SOFT or HARD CORE0_INIT = INIT_IMX ; init section for iMX CORE0_FLASH0 = FLASH_RT1064_F2 CORE0_FLASH1 = FLASH_RT1064_F1 CORE0_WORKSPACE = 0x20200000, 0x4000 ; workspace for agent programming ; COREn_SWO , ;CORE0_SWO = 31, 4601 CORE0_PATH = "tftp://192.168.3.5" ; default path [INIT_IMX] mem write 0xE000ED14 0x00040200 ; SCB->CCR - disable I/D-cache mem write 0xE000EF50 0x00000000 ; SCB->ICIALLU - invalidate I-cache mem write 0xE000EF74 0x00000000 ; SCB->DCCISW mem write 0xE000ED94 0x00000000 ; MPU_CTRL, disable MPU mem write 0xE000ED04 0x02000000 ; Force ICSR:PENDSTCLR mem write 0xE000E010 0x00000000 ; Disable SYSTICK ; sysinit - setup SDRAM mem write 0x400FC068 0xFFFFFFFF mem write 0x400FC06C 0xFFFFFFFF mem write 0x400FC070 0xFFFFFFFF mem write 0x400FC074 0xFFFFFFFF mem write 0x400FC078 0xFFFFFFFF mem write 0x400FC07C 0xFFFFFFFF mem write 0x400FC080 0xFFFFFFFF mem write 0x400D8030 0x00002001 mem write 0x400D8100 0x001D0000 mem write 0x400FC014 0x00010D40 ; CBCMR mem write 0x400FC018 0x35AE8304 ; default ;mem write 0x400FC018 0x15AE8104 ; PODF=div-by-2 and CLK_SEL=1==PLL3_PFD0 (as eCos) ;mem write 0x400FC018 0xF5AE8104 ; PODF=div-by-8 and CLK_SEL=1==PLL3_PFD0 ; CSCMR1 mem write 0x400FC01C 0x67930001 mem write 0x400FC024 0x06490B03 mem write 0x401F8014 0x00000000 mem write 0x401F8018 0x00000000 mem write 0x401F801C 0x00000000 mem write 0x401F8020 0x00000000 mem write 0x401F8024 0x00000000 mem write 0x401F8028 0x00000000 mem write 0x401F802C 0x00000000 mem write 0x401F8030 0x00000000 mem write 0x401F8034 0x00000000 mem write 0x401F8038 0x00000000 mem write 0x401F803C 0x00000000 mem write 0x401F8040 0x00000000 mem write 0x401F8044 0x00000000 mem write 0x401F8048 0x00000000 mem write 0x401F804C 0x00000000 mem write 0x401F8050 0x00000000 mem write 0x401F8054 0x00000000 mem write 0x401F8058 0x00000000 mem write 0x401F805C 0x00000000 mem write 0x401F8060 0x00000000 mem write 0x401F8064 0x00000000 mem write 0x401F8068 0x00000000 mem write 0x401F806C 0x00000000 mem write 0x401F8070 0x00000000 mem write 0x401F8074 0x00000000 mem write 0x401F8078 0x00000000 mem write 0x401F807C 0x00000000 mem write 0x401F8080 0x00000000 mem write 0x401F8084 0x00000000 mem write 0x401F8088 0x00000000 mem write 0x401F808C 0x00000000 mem write 0x401F8090 0x00000000 mem write 0x401F8094 0x00000000 mem write 0x401F8098 0x00000000 mem write 0x401F809C 0x00000000 mem write 0x401F80A0 0x00000000 mem write 0x401F80A4 0x00000000 mem write 0x401F80A8 0x00000000 mem write 0x401F80AC 0x00000000 mem write 0x401F80B0 0x00000010 mem write 0x401F80B4 0x00000000 mem write 0x401F80B8 0x00000000 mem write 0x401F8204 0x000110F9 mem write 0x401F8208 0x000110F9 mem write 0x401F820C 0x000110F9 mem write 0x401F8210 0x000110F9 mem write 0x401F8214 0x000110F9 mem write 0x401F8218 0x000110F9 mem write 0x401F821C 0x000110F9 mem write 0x401F8220 0x000110F9 mem write 0x401F8224 0x000110F9 mem write 0x401F8228 0x000110F9 mem write 0x401F822C 0x000110F9 mem write 0x401F8230 0x000110F9 mem write 0x401F8234 0x000110F9 mem write 0x401F8238 0x000110F9 mem write 0x401F823C 0x000110F9 mem write 0x401F8240 0x000110F9 mem write 0x401F8244 0x000110F9 mem write 0x401F8248 0x000110F9 mem write 0x401F824C 0x000110F9 mem write 0x401F8250 0x000110F9 mem write 0x401F8254 0x000110F9 mem write 0x401F8258 0x000110F9 mem write 0x401F825C 0x000110F9 mem write 0x401F8260 0x000110F9 mem write 0x401F8264 0x000110F9 mem write 0x401F8268 0x000110F9 mem write 0x401F826C 0x000110F9 mem write 0x401F8270 0x000110F9 mem write 0x401F8274 0x000110F9 mem write 0x401F8278 0x000110F9 mem write 0x401F827C 0x000110F9 mem write 0x401F8280 0x000110F9 mem write 0x401F8284 0x000110F9 mem write 0x401F8288 0x000110F9 mem write 0x401F828C 0x000110F9 mem write 0x401F8290 0x000110F9 mem write 0x401F8294 0x000110F9 mem write 0x401F8298 0x000110F9 mem write 0x401F829C 0x000110F9 mem write 0x401F82A0 0x000110F9 mem write 0x401F82A4 0x000110F9 mem write 0x401F82A8 0x000110F9 mem write 0x402F0000 0x10000004 mem write 0x402F0008 0x00030524 mem write 0x402F000C 0x06030524 mem write 0x402F0010 0x8000001B mem write 0x402F0014 0x8200001B mem write 0x402F0018 0x8400001B mem write 0x402F001C 0x8600001B mem write 0x402F0020 0x90000021 mem write 0x402F0024 0xA0000019 mem write 0x402F0028 0xA8000017 mem write 0x402F002C 0xA900001B mem write 0x402F0030 0x00000021 mem write 0x402F0004 0x000079A8 mem write 0x402F0040 0x00000F31 mem write 0x402F0044 0x00652922 mem write 0x402F0048 0x00010920 mem write 0x402F004C 0x50210A08 mem write 0x402F0080 0x00000021 mem write 0x402F0084 0x00888888 mem write 0x402F0094 0x00000002 mem write 0x402F0098 0x00000000 mem write 0x402F0090 0x80000000 mem write 0x402F009C 0xA55A000F ; CHECK: 0x402F003C 0x00000001 SEMC_INTR infinite poll : (0 != (*address & mask)) : bit0 IPCMDDONE wait 200 mem write 0x402F0090 0x80000000 mem write 0x402F009C 0xA55A000C ; CHECK: 0x402F003C 0x00000001 SEMC_INTR infinite poll : (0 != (*address & mask)) : bit0 IPCMDDONE wait 200 mem write 0x402F0090 0x80000000 mem write 0x402F009C 0xA55A000C ; CHECK: 0x402F003C 0x00000001 SEMC_INTR infinite poll : (0 != (*address & mask)) : bit0 IPCMDDONE wait 200 mem write 0x402F00A0 0x00000033 mem write 0x402F0090 0x80000000 mem write 0x402F009C 0xA55A000A ; CHECK: 0x402F003C 0x00000001 SEMC_INTR infinite poll : (0 != (*address & mask)) : bit0 IPCMDDONE wait 200 mem write 0x402F004C 0x50210A09 ; Assign all flexram to OCRAM: mem write 0x400AC040 0x00200007 mem write 0x400AC044 0x55555555 ; Setup FlexSPI1 pins: ; FLEXSPI_A_DQS ;mem write 0x401F816C 0x00000001 ;mem write 0x401F82E0 0x000010F1 ; FLEXSPI_A_SCLK (SD_B1_07) mem write 0x401F81F0 0x00000001 mem write 0x401F84C8 0x00000000 mem write 0x401F83E0 0x000010F1 ; FLEXSPI_A_SS0 (SD_B1_06) mem write 0x401F81EC 0x00000001 mem write 0x401F83DC 0x000010F1 ; FLEXSPI_A_DATA0 (SD_B1_08) mem write 0x401F81F4 0x00000001 mem write 0x401F84A8 0x00000000 mem write 0x401F83E4 0x000010F1 ; FLEXSPI_A_DATA1 (SD_B1_09) mem write 0x401F81F8 0x00000001 mem write 0x401F84AC 0x00000000 mem write 0x401F83E8 0x000010F1 ; FLEXSPI_A_DATA2 (SD_B1_10) mem write 0x401F81FC 0x00000001 mem write 0x401F84B0 0x00000000 mem write 0x401F83EC 0x000010F1 ; FLEXSPI_A_DATA3 (SD_B1_11) mem write 0x401F8200 0x00000001 mem write 0x401F84B4 0x00000000 mem write 0x401F83F0 0x000010F1 ; force same clk selection as FlexSPI1 - and also slowest divider mem write 0x400FC018 0xF5AE8104 ; Setup FlexSPI2 pins: ; TODO: commented out following to leave pins as ROM bootloader configures - which seems OK ; FLEXSPI2_A_DQS (SPI_B0_09 ALT0) ; GPIO_SPI_B0_09 MUX=0x00000005 CTL=0x000000F1 : MUX_MODE=5 GPIO10_IO09 MAX(150MHz..200MHz) [1.8V:43/43-Ohm 3.3V:40/26-Ohm] SRE ;mem write 0x401F8680 0x00000000 ;mem write 0x401F86D8 0x000000F1 ; FLEXSPI2_A_SS0_B (SPI_B1_06 ALT0) ; GPIO_SPI_B1_06 MUX=0x00000000 CTL=0x000000F1 : MUX_MODE=0 FLEXSPI2_A_SS0_B MAX(150MHz..200MHz) [1.8V:43/43-Ohm 3.3V:40/26-Ohm] SRE ;mem write 0x401F86AC 0x00000000 ;mem write 0x401F8704 0x000000F1 ; FLEXSPI2_A_SCLK (SPI_B0_08 ALT0) ; GPIO_SPI_B0_08 MUX=0x00000010 CTL=0x000000F1 : SION MUX_MODE=0 FLEXSPI2_A_SCLK MAX(150MHz..200MHz) [1.8V:43/43-Ohm 3.3V:40/26-Ohm] SRE ;mem write 0x401F867C 0x00000010 ;mem write 0x401F86D4 0x000000F1 ; FLEXSPI2_A_DATA0 (SPI_B0_02 ALT0) ; GPIO_SPI_B0_02 MUX=0x00000000 CTL=0x000000F1 : MUX_MODE=0 FLEXSPI2_A_DATA00 MAX(150MHz..200MHz) [1.8V:43/43-Ohm 3.3V:40/26-Ohm] SRE ;mem write 0x401F8664 0x00000000 ;mem write 0x401F86BC 0x000000F1 ; FLEXSPI2_A_DATA1 (SPI_B1_03 ALT0) ; GPIO_SPI_B1_03 MUX=0x00000000 CTL=0x000000F1 : MUX_MODE=0 FLEXSPI2_A_DATA01 MAX(150MHz..200MHz) [1.8V:43/43-Ohm 3.3V:40/26-Ohm] SRE ;mem write 0x401F86A0 0x00000000 ;mem write 0x401F86F8 0x000000F1 ; FLEXSPI2_A_DATA2 (SPI_B1_02 ALT0) ; GPIO_SPI_B1_02 MUX=0x00000000 CTL=0x000000F1 : MUX_MODE=0 FLEXSPI2_A_DATA02 MAX(150MHz..200MHz) [1.8V:43/43-Ohm 3.3V:40/26-Ohm] SRE ;mem write 0x401F869C 0x00000000 ;mem write 0x401F86F4 0x000000F1 ; FLEXSPI2_A_DATA3 (SPI_B0_10 ALT0) ; GPIO_SPI_B0_10 MUX=0x00000000 CTL=0x000000F1 : MUX_MODE=0 FLEXSPI2_A_DATA03 MAX(150MHz..200MHz) [1.8V:43/43-Ohm 3.3V:40/26-Ohm] SRE ;mem write 0x401F8684 0x00000000 ;mem write 0x401F86DC 0x000000F1 ; FLEXSPI2_MCR0 ;mem write 0x402A4000 0xFFFF8410 [FLASH_RT1064_F2] ; i.MX RT1064 SiP W25Q32JV : QSPI 32M NOR flash, FlexSPI2 (bootable) SPI_CS = 1 CHIP = SPI25_FLASH CPU = NXP_FSPI_RT10XX ; flash chip ACCESS_METHOD = AGENT ; use agent programming AUTO_ERASE = NO ; erase before program FILE = test512k.bin 0x0000000 ; file to program [FLASH_RT1064_F1] ; MIMXRT1064-EVK U33 IS25WP064AJBLE : QSPI 64M NOR flash, FlexSPI1 SPI_CS = 0 CHIP = SPI25_FLASH CPU = NXP_FSPI_RT10XX ; flash chip ACCESS_METHOD = AGENT ; use agent programming AUTO_ERASE = NO ; erase before program FILE = test512k.bin 0x0000000 ; file to program [SERIAL] ; serial port configuration BAUD = 115200 STOP_BITS = 1 PARITY = NONE TCP_PORT = 0 [TELNET] PROMPT = "rt1064evk_swd> " ;BACKSPACE = 127 ; comment out for autodetect [DISPLAY] BRIGHTNESS = 20 ; LED indicator brightness VOLUME = 25 ; beeper volume [ACTIONS] ; user defined scripts ;AUTORUN = 2 ; executed on every target connect 1 = erase 2 = prog 3 = dump_ram 4 = dump_flash [erase] ; erase flash flash erase [prog] ; program flash flash prog